MOS (metal—oxide film—semiconductor layer) field-effect transistors are widely used as basic elements in semiconductor devices. In ICs (integrated circuits) with a high breakdown voltage, MOS transistors are used that can be driven at a medium to high voltage of around 10 V or higher, for example (hereafter called high breakdown voltage MOS transistors).
FIG. 9 is a schematic cross section that shows the constitution of a high breakdown voltage MOS transistor and its production processes.
Gate insulating film 101, made of silicon oxide, for example, is formed on an active region that will be the channel region on p-type semiconductor substrate 100, which is divided by an element separating and insulating film, not shown. Gate electrode 102, made of polysilicon, for example, is formed as a top layer.
Lightly doped region (LDD dispersion layer) 103, which contains an n-type impurity at a low concentration, and heavily doped region (source-drain dispersion layer) 105, that contain an n-type impurity at a high concentration, are formed in semiconductor substrate 100 at both sides of gate electrode 102. Here, lightly doped region (LDD dispersion layer) 103 is a layer furnished to moderate the drain electrical field.
In a MOS transistor with the aforementioned constitution, offset (d), which is the distance between gate electrode 102 and heavily doped region 105, is around 0.5 μm, for example, and offset d must be set to approximately this dimension or greater to ensure high breakdown voltage characteristics for the transistor.
The manufacturing method for the aforementioned MOS transistor will now be explained.
An element separating and insulating film, not shown, which divides the active regions that will be channel regions, is formed on p-type semiconductor substrate 100; gate insulating film 101 made of silicon oxide is formed by thermal oxidation, for example; polysilicon is further deposited by a CVD (chemical vapor deposition) method, for example; the resist film for the gate electrode pattern is patterned with a photolithography process; and etching, such as RIE (reaction ion etching) is applied to pattern the gate electrode shape to produce gate electrode 102.
Next an n-type impurity is ion implanted at a low concentration using gate electrode 102 as the mask to form lightly doped region 103.
Next resist film 104 is formed so that offset d from gate electrode 102 will be a prescribed value, an n-type impurity DT is ion implanted at a high concentration using said resist film 104 as the mask, and heavily doped region 105 is formed.
In the aforementioned manufacturing method, offset d, which is the distance between gate electrode 102 and heavily doped region 105, is controlled by the position at which the resist film that serves as a mask is formed, so that misaligning the mask has a significant effect on breakdown voltage characteristics, and this is a problem.
On the other hand, the constitution shown in FIG. 10 is widely used as a low voltage MOS transistor when using sub-micron rules or quarter-micron rules.
Gate insulating film 201, made of silicon oxide, for example, is formed on the active region that will be the channel formation region of p-type semiconductor substrate 200 that is divided ay an element separating and insulating film, not shown. Gate electrode 202 made of polysilicon, for example, is formed as a top layer.
Side wall insulating film 204, made of silicon oxide, for example, is formed at both sides of gate electrode 202. Lightly doped region 203, that contains an n-type impurity at a low concentration, is formed in semiconductor substrate 200 on both sides of gate electrode 202, corresponding to the region below side wall insulating film 204, and heavily doped region 205, that contains an n-type impurity at a high concentration, is formed in semiconductor substrate 200, corresponding to both regions outside of side wall insulating film 204.
The manufacturing method for the aforementioned MOS transistor will now be explained.
An element separating and insulating film, not shown, which divides the active regions that will be the channel regions is formed on p-type semiconductor substrate 200; gate insulating film 201, made of silicon oxide, is formed by thermal oxidation, for example; polysilicon is additionally deposited with CVD, for example; the resist film for the gate electrode pattern is patterned with a photolithography process; and etching, such as RIE, is applied to pattern the gate electrode shape and produce gate electrode 202.
Next, an n-type impurity is ion implanted at a low concentration using gate electrode 202 as a mask and lightly doped region 203 is formed.
Next a silicon oxide film is deposited by CVD, for example, over the entire surface, and then this silicon oxide film is removed by etching back the entire surface to leave silicon oxide in the regions at both sides of gate electrode 202, and side wall insulating film 204 is formed.
Next n-type impurity DT is ion implanted at a high concentration using side wall insulating film 204 as the mask, and heavily doped region 205 is formed.
In the aforementioned manufacturing method, offset d, which is the distance between gate electrode 202 and heavily doped region 205, can be controlled by the width of side wall insulating film 204.
The width of side wall insulating film 204 can be controlled by the deposition width of the silicon oxide that will form side wall insulating film 204. Because of this, the MOS transistor can be manufactured to keep offset d fixed, that is, to keep the characteristics fixed.
However, if a high breakdown voltage MOS transistor is constituted as shown in FIG. 9 and a low breakdown voltage MOS transistor is constituted as shown in FIG. 10, in a semiconductor device that has the aforementioned high breakdown voltage MOS transistor and low breakdown voltage MOS transistor on the same substrate, the manufacturing processes for the two transistors are not compatible, and there still remains the problem that the effect on breakdown voltage characteristics due to misalignment of the mask is significant in the high breakdown voltage MOS transistor.
A method for constituting both a high breakdown voltage MOS transistor and a low voltage MOS transistor as shown in FIG. 10 has been considered. With this method, it is easy to keep offset d fixed even in the high breakdown voltage MOS transistor.
However, if higher voltages for high breakdown voltage MOS transistors and further miniaturization of low voltage MOS transistors are promoted, a side wall insulating film that satisfies requirements for both transistors cannot be realized.
Thus higher voltages for high breakdown voltage MOS transistors and further miniaturization of low voltage MOS transistors cannot be accommodated.
This invention was devised taking the aforementioned circumstances into consideration. Thus the purpose of this invention is to provide a semiconductor device, and a manufacturing method therefor, where the offset can easily be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate higher voltages for high breakdown voltage MOS transistors and further miniaturization of low voltage MOS transistors.